The present invention relates to a pipeline-operating type memory system, and more particularly to the pipeline-operating type memory system which may be adaptively suitable if the number of data pieces read from a memory array is larger than the number of output bits.
In general, a pipeline-operating type signal processing means have been frequently used in a logic (Large Scaled Integration) configuring a microprocessor or the like. The application of such a means into a memory LSI for configuring a high-performance memory has been disclosed in the U.S. Pat. No. 4,685,088. This Patent specification discloses that one piece of data for a column address is selected from all the data held in the latch circuit by a multiplexor. That is, the description is oriented to a function of selecting a column.